يعرض 1 - 8 نتائج من 8 نتيجة بحث عن '"Resistor"', وقت الاستعلام: 0.84s تنقيح النتائج
  1. 1

    المصدر: IEEE Electron Device Letters. 41:353-356

    الوصف: Memristor emerges as the key enabler for neural network accelerator. Here, we demonstrate high-precision symmetric weight update in a one transistor one resistor (1T1R) structure Ti/HfO2/TiN memristor using a gate voltage ramping method, with over 120-level states and low variation (< 4%). Incorporating all experimental non-idealities, the proposed mixed hardware-software convolutional neural network demonstrates over 92.79% online learning accuracy (against software equivalent 98.45%) for MNIST recognition task. The network also shows robustness to input image noises, array yield, and retention issues.

  2. 2

    المصدر: Khitun, Alexander G.; Geremew, Adane K.; & Balandin, Alexander A.(2018). Transistor-Less Logic Circuits Implemented With2-D Charge Density Wave Devices. IEEE ELECTRON DEVICE LETTERS, 30(9). UC Office of the President: UC Lab Fees Research Program (LFRP); a funding opportunity through UC Research Initiatives (UCRI). Retrieved from: http://www.escholarship.org/uc/item/5989z5c6

    الوصف: We propose logic gates and circuits implemented with 2-D charge density wave (CDW) devices, which operate at room temperature. The 1T-TaS2 charge density wave devices exhibit a voltage triggered phase transition between the nearly commensurate and incommensurate CDW states, which is accompanied by an abrupt change of the resistance and hysteresis. The unique output characteristics of such devices allow for building logic gates and circuits without any transistors. Using the experimentally measured current–voltage characteristics, we model and numerically simulate the performance of the inverter and the OR logic gates consisting of CDW devices and regular resistors. Owing to the radiation-hard nature of the CDW devices and absence of transistors, the proposed circuits can be utilized in various harsh environments on earth or outer space.

    وصف الملف: application/pdf

  3. 3

    المؤلفون: Yu Han, Kei May Lau, Qiang Li

    المصدر: IEEE Electron Device Letters. 38:556-559

    الوصف: We report the fabrication and characterization of a GaAs fin-array tunneling trigger monolithically integrated on an exact (001) silicon substrate. A Schmitt-trigger-like behavior was observed under double sweep condition by connecting the tunnel diode with an on-chip load resistor. The tunneling trigger circuit was studied using load line analysis. Critical parameters of the circuit were extracted. We found that the circuit hysteresis can be tuned by tailoring of the diode dimensions and load resistor values.

    وصف الملف: application/pdf

  4. 4

    المؤلفون: Guo-Qiang Lo, Fei Sun, Ning Duan

    المصدر: IEEE Electron Device Letters. 34:653-655

    الوصف: A novel structure of silicon photomultiplier (SiPM) is reported. In this structure, a vertical bulk-Si quenching resistor is introduced to replace the poly-Si resistor in the SiPM cell, which can help to improve the fill factor of the SiPM for more efficient photon detection. A current-blocking layer is inserted into the resistor layer to reduce the cross-section of the resistor so that the necessary high quenching resistance can be achieved by the thin resistor layer. The performance of the SiPM cell is confirmed by simulation. The vertical bulk-Si resistors are fabricated and characterized. According to the $I{-}V$ measurements, the structures achieved show good resistor properties. An equivalent quenching resistance in the order of $10^{5}~\Omega$ is observed in a 1- $\mu{\rm m}$ -thick resistor.

  5. 5

    المصدر: IEEE Electron Device Letters. 14:152-154

    الوصف: Self-heating (SH) in submicrometer CMOS transistors operated at liquid-helium temperature and under different bias conditions was experimentally verified by measuring the temperature T/sub Si/ in the proximity of the device. T/sub Si/ was measured by using a silicon resistor, placed in the same bulk nearby the device under test, as a temperature sensor. It was found that the heat generated by the NMOS transistor of a CMOS inverter structure penetrates deep into the substrate and reduces very strongly the n-well impedance, giving rise to large variations in the kink of the I/sub drain/-V/sub drain/ characteristics of the neighbor PMOS transistor. Experimental results confirm that SH must not be underestimated when characterizing and modeling low-temperature device operation. >

  6. 6

    المؤلفون: D. Heidel, T.R. Gheewala

    المصدر: IEEE Electron Device Letters. 3:93-96

    الوصف: A self-biasing network for Josephson logic circuits that permits wide variations in junction critical currents, resistors, and power supply voltage is presented. The self-biasing network automatically switches resistors in or out to make the gate currents track with the critical currents of the logic gates. Results of Monte Carlo statistical analyses of the tolerances of this scheme are presented as a function of amount of correlation between the critical currents of the logic device and the biasing network, amount of systematic variation on a chip, and number of junctions used in the biasing network. Results indicate that almost a factor of two larger variations in the critical currents of the Josephson junctions can be tolerated when the self-biasing network is used, without adverse impact on the gate delays and the power dissipation.

  7. 7

    المصدر: IEEE Electron Device Letters. 9:122-124

    الوصف: Flip-flop and frequency-doubling operations are demonstrated, using a simple circuit that combines a resistor with a three-terminal negative-resistance device. The device is a series integration of resonant-tunneling heterostructure with a field-effect transistors. Results, obtained at 77 K, are presented for two samples that were grown by metalorganic chemical vapor deposition. >

  8. 8

    المصدر: IEEE Electron Device Letters. 6:594-596

    الوصف: Two-dimensional (2-D) electron-gas carrier mobiliy in 1µm gate-length modulation-doped FET's has been determined as a function of the gate bias voltage. The measurement technique utilizes a small-signal gate voltage excitation and probes the true channel conductance by directly eliminating the source and drain series resistance effects. The mobility is extracted by combining the channel conductance data with the CV data and its variation with gate bias voltage is indicative of the variation of the effectiveness of screening of the ionized impurities and the quality of the MBE-grown GaAs buffer layer.