المؤلفون: Dinesh Bhatia, Parivallal Kannan

المصدر: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1523-1534

مصطلحات موضوعية: Router, Interconnection, Computer science, business.industry, Design flow, Integrated circuit, Computer Graphics and Computer-Aided Design, law.invention, Application-specific integrated circuit, law, Embedded system, Hardware_INTEGRATEDCIRCUITS, Benchmark (computing), Electrical and Electronic Engineering, Routing (electronic design automation), Physical design, business, Field-programmable gate array, Software, Computer hardware

الوصف: Interconnect planning is becoming an important design issue for large field programmable gate array (FPGA)-based designs. One of the most important issues for planning interconnection is the ability to reliably predict the routing requirements of a given design. In this paper, a new methodology, called fast generic routability estimation for placed FPGA circuits (fGREP), for fast and reliable estimation of routing requirements for placed circuits on island-style FPGAs, is introduced. This method is based on newly derived detailed router characterizations that are introduced in this paper. It is observed that the router has a limited number of available routing elements to use and the number is proportional to the distance from a net's terminal. This is defined as the routing flexibility and an estimate for interconnect requirements is derived from it. This method is able to predict the distribution of interconnect requirements, with very fine granularity, across the entire device. The interconnect-distribution information is used to estimate congestion and total wirelength. Multiterminal nets are efficiently handled, without the need for net decomposition. This method is generic enough to enable its usage with any standard FPGA place-and-route design flow and for any island-style FPGA architecture. The method is also applicable to application-specific integrated circuit (ASIC) design flows. Experimental results on a large set of standard benchmark examples show that the estimates obtained here closely match with the detailed routing results of the state-of-the-art router PathFinder , as implemented in the well-known FPGA physical design suite VPR.

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::4b604c187d481e773cfc1f9b69808061
https://doi.org/10.1109/tcad.2005.857312

المؤلفون: Parivallal Kannan, Shankar Balachandran, Dinesh Bhatia

المصدر: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12:381-385

مصطلحات موضوعية: Router, Engineering, business.industry, Integrated circuit layout, Application-specific integrated circuit, Computer engineering, Hardware and Architecture, Embedded system, Metric (mathematics), Rent's rule, Hardware_INTEGRATEDCIRCUITS, Benchmark (computing), Electronic design automation, Electrical and Electronic Engineering, Routing (electronic design automation), business, Software

الوصف: Interconnect management is a critical design issue for large field-programmable gate arrays (FPGA) based designs. One of the most important issues for planning interconnection is the ability to reliably and efficiently predict the interconnect requirements of a given design on a given FPGA architecture. Many interconnect estimation methods have been reported so far and the estimation problem is also under active research. From a CAD tool deployment point of view, comparing these estimation methods is very difficult because of the different reporting methods used by the authors. We make an argument for and propose a new uniform reporting metric, based on comparing the estimates with the results of an actual detailed router on both local and global levels. We then compare some of the well known and promising interconnect estimation methods using our new metric on a large number of benchmark circuits.

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::b61c111d83b6d0928f34825324ec215f
https://doi.org/10.1109/tvlsi.2004.825865

المؤلفون: Balaraman Ravindran, R. Manimegalai, V. Muralidharan, Dinesh Bhatia, V. Kamakoti, E. Siva Soumya

المصدر: VLSI Design

مصطلحات موضوعية: Reduction (complexity), Very-large-scale integration, Support vector machine, Computer engineering, Computer science, Hardware_INTEGRATEDCIRCUITS, Benchmark (computing), Electronic engineering, Reinforcement learning, Routing (electronic design automation), Placement, Integrated circuit layout

الوصف: The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed on 2D-FPGA. This results in a considerable reduction in total interconnect length. Reduced wire length eventually leads to reduction in delay and hence improved performance and speed. Design of an efficient placement and routing algorithm for 3D-FPGA that fully exploits the above mentioned advantage is a problem of deep research and commercial interest. In this paper, an efficient placement and routing algorithm is proposed for 3D-FPGAs which yields better results in terms of total interconnect length and channel-width. The proposed algorithm employs two important techniques, namely, reinforcement learning (RL) and support vector machines (SVMs), to perform the placement. The proposed algorithm is implemented and tested on standard benchmark circuits and the results obtained are encouraging. This is one of the very few instances where reinforcement learning is used for solving a problem in the area of VLSI.

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::93b836ddcbda7abc0142be97a0ce2c96
https://doi.org/10.1109/icvd.2005.137