المؤلفون: Chaurasiya, Rohit B., Shrestha, Rahul

المصدر: 2019 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2019 IEEE International Symposium on. :1-5 May, 2019

Relation: 2019 IEEE International Symposium on Circuits and Systems (ISCAS)

المؤلفون: Hawich, Malte^Aff10, Rumpeltin, Nico^Aff10, Rücker, Malte^Aff11, Stuckenberg, Tobias^Aff10, Blume, Holger^Aff10

المساهمون: Goos, Gerhard, Founding Editor^Aff1, Hartmanis, Juris, Founding Editor^Aff2, Bertino, Elisa, Editorial Board Member^Aff3, Gao, Wen, Editorial Board Member^Aff4, Steffen, Bernhard, Editorial Board Member^Aff5, Yung, Moti, Editorial Board Member^Aff6, Silvano, Cristina, editor^Aff7, Pilato, Christian, editor^Aff8, Reichenbach, Marc, editor^Aff9

المصدر: Embedded Computer Systems: Architectures, Modeling, and Simulation : 23rd International Conference, SAMOS 2023, Samos, Greece, July 2–6, 2023, Proceedings. 14385:255-268

المؤلفون: Benjamin, J.L., Funnell, A., Watts, P.M., Thomsen, B.

المصدر: 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI) HOTI High-Performance Interconnects (HOTI), 2017 IEEE 25th Annual Symposium on. :41-48 Aug, 2017

Relation: 2017 IEEE 25th Annual Symposium on High-Performance Interconnects (HOTI)

المؤلفون: Ugurdag, H. Fatih, Bayram, Anil, Levent, Vecdi Emre, Goren, Sezer

المصدر: 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH) Computer Arithmetic (ARITH), 2016 IEEE 23nd Symposium on. :1-7 Jul, 2016

Relation: 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH)

المؤلفون: Taraate, Vaibbhav^Aff2

المساهمون: Taraate, Vaibbhav^Aff1

المصدر: Logic Synthesis and SOC Prototyping : RTL Design using VHDL. :47-67

المؤلفون: Nikolic, Milos, Katona, Mihajlo

المصدر: Proceedings of Papers 5th European Conference on Circuits and Systems for Communications (ECCSC'10) Circuits and Systems for Communications (ECCSC), 2010 5th European Conference on. :131-134 Nov, 2010

Relation: 2010 5th European Conference on Circuits and Systems for Communications (ECCSC)

المؤلفون: Taraate, Vaibbhav^Aff2

المساهمون: Taraate, Vaibbhav^Aff1

المصدر: Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog. :25-50

المؤلفون: Ugurdag, H.F., de Dinechin, F., Gener, Y.S., Goren, S., Didier, L.

المصدر: IEEE Transactions on Computers IEEE Trans. Comput. Computers, IEEE Transactions on. 66(12):2097-2110 Dec, 2017

المؤلفون: Cushon, K., Larsson-Edefors, P., Andrekson, P.

المصدر: Journal of Lightwave Technology J. Lightwave Technol. Lightwave Technology, Journal of. 34(18):4304-4311 Sep, 2016

المؤلفون: Radosavljevic, P., Yuanbin Guo, Cavallaro, J.

المصدر: IEEE Journal on Selected Areas in Communications IEEE J. Select. Areas Commun. Selected Areas in Communications, IEEE Journal on. 27(8):1318-1330 Oct, 2009