نتائج البحث - "Duk-ha Park"

1

مؤتمر

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

المؤلفون: Kyu-hyoun Kim, Uksong Kang, Hoe-Ju Chung, Duk-Ha Park, Woo-Seop Kim, Young-Chan Jang, Moonsook Park, Hoon Lee, Jin-Young Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo Sun Choi, Changhyun Kim

المصدر: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International. :527-536 2006

Relation: 2006 IEEE International Solid State Circuits Conference

Full Text Finder

2

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

المصدر: IEEE Journal of Solid-State Circuits. 56:212-224

مصطلحات موضوعية: Synchronization (alternating current), Interleaving, Computer science, Duty cycle, Control theory, Skew, Electrical and Electronic Engineering, Dram, Electronic circuit, Voltage, Power (physics)

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::14d89c19ed61d41454dba483b0be2a36
https://doi.org/10.1109/jssc.2020.3017775

3

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

المؤلفون: Hyong-Ryol Hwang, Young-Soo Sohn, Young Hoon Son, Seungseob Lee, Seung-Jun Bae, Hyuck-Joon Kwon, Jung-Bae Lee, Byongwook Na, Chang-Kyo Lee, Young-Hwa Kim, Dongkeon Lee, Duk-ha Park, Daesik Moon, Kwang-Il Park, Tae-Young Oh, Youn-sik Park, Kyung-Soo Ha

المصدر: IEEE Journal of Solid-State Circuits. 55:157-166

مصطلحات موضوعية: Dynamic voltage frequency scaling, Computer science, business.industry, 020208 electrical & electronic engineering, Bandwidth (signal processing), Electrical engineering, 02 engineering and technology, Chip, law.invention, law, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Resistor, business, Dram, Voltage, Leakage (electronics)

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::a3c0d249a308f28f1535a7ab42eb92fc
https://doi.org/10.1109/jssc.2019.2938396

4

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

المصدر: ISSCC

مصطلحات موضوعية: Boosting (machine learning), business.industry, Computer science, law, Transistor, Skew, Process (computing), business, Computer hardware, Dram, Power (physics), Jitter, law.invention

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::c2d3bf8b7cf0e24bdfbbca56a91c30e7
https://doi.org/10.1109/isscc19947.2020.9062914

5

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

المصدر: ISSCC

مصطلحات موضوعية: Non target, Computer science, business.industry, 020208 electrical & electronic engineering, Bandwidth (signal processing), 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, business, 5G, Computer hardware, Dram

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::3f8b77e89febd51cb1428fa3986dea1f
https://doi.org/10.1109/isscc.2019.8662509

6

A 31 ns Random Cycle VCAT-Based 4F$^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

المصدر: IEEE Journal of Solid-State Circuits. 45:880-888

مصطلحات موضوعية: Engineering, Dynamic random-access memory, Sense amplifier, business.industry, Transistor, Integrated circuit, Chip, law.invention, Design for manufacturability, Non-volatile memory, law, Electronic engineering, Electrical and Electronic Engineering, business, Dram

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::3787a1b86ee135b11b8596eb33058671
https://doi.org/10.1109/jssc.2010.2040229

7

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

المؤلفون: Jung Sunwoo, Hoon Lee, Woo-Seop Kim, Moon-Sook Park, Kyu-hyoun Kim, Young-Chan Jang, Hoe-ju Chung, Chang-Hyun Kim, Su-Jin Chung, Duk-ha Park, Jae-Kwan Kim, Jin-Young Kim, Hyun-Kyung Kim, Hwan-Wook Park, Uk-Song Kang, Young-Taek Lee, Joo Sun Choi, Kee-Won Kwon, Hyung-seuk Kim

المصدر: ISSCC

مصطلحات موضوعية: Input/output, Dynamic random-access memory, business.industry, Cycles per instruction, Computer science, Bubble, Parallel computing, Integrated circuit, Chip, law.invention, law, Transfer (computing), Code (cryptography), Bandwidth (computing), Electrical and Electronic Engineering, business, Error detection and correction, Computer hardware

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::459383a88b892d96879ad94fa0d7818a
https://doi.org/10.1109/jssc.2006.888297

8

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

المؤلفون: null Kyu-hyoun Kim, null Uksong Kang, null Hoe-Ju Chung, null Duk-Ha Park, null Woo-Seop Kim, null Young-Chan Jang, null Moonsook Park, null Hoon Lee, null Jin-Young Kim, null Jung Sunwoo, null Hwan-Wook Park, null Hyun-Kyung Kim, null Su-Jin Chung, null Jae-Kwan Kim, null Hyung-Seuk Kim, null Kee-Won Kwon, null Young-Taek Lee, null Joo Sun Choi, null Changhyun Kim

المصدر: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::b9f8b2954c6651dbe8e4120ad7fcd6cb
https://doi.org/10.1109/isscc.2006.1696089

9

Highly manufacturable 100 nm 6T low power SRAM with single poly-Si gate technology

المؤلفون: Sunae Seo, Hyung-Guel Kim, Kun-Ho Kwak, Duk-ha Park, B.J. Hwang, Yang-Soo Son, K.N. Kim, Kyoung-Min Koh, J.H. Jang, J.Y. Lee

المصدر: 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

مصطلحات موضوعية: Hardware_MEMORYSTRUCTURES, Materials science, business.industry, Subthreshold conduction, Transistor, Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, PMOS logic, law.invention, Process variation, law, MOSFET, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, Static random-access memory, business, NMOS logic, Hardware_LOGICDESIGN, Leakage (electronics)

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::e7d80f29d54e6f8c3aec6f18ea1c41a7
https://doi.org/10.1109/vtsa.2003.1252553

10

دورية أكاديمية

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.

المؤلفون: Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, Duk-Ha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo Sun Choi, Changhyun Kim

المصدر: IEEE Journal of Solid-State Circuits; Jan2010, Vol. 45 Issue 1, p111-119, 9p

مصطلحات موضوعية: DYNAMIC random access memory, NARROW gap semiconductors, BIT rate, SPEED limits, QUANTITATIVE research

Full Text Finder

تنقيح النتائج