نتائج البحث - "Keun-Soo Song"

1

مؤتمر

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

المصدر: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. :140-141,141a Feb, 2009

Relation: 2009 IEEE International Solid-State Circuits Conference - (ISSCC)

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2

مؤتمر

A single-loop DLL using an OR-AND duty-cycle correction technique

المؤلفون: Keun-Soo Song, Cheul-Hee Koo, Nak-Kyu Park, Kim, Kwan-Weon, Choi, Young-Jung, Jin-Hong Ahn, Byong-Tae Chung

المصدر: 2008 IEEE Asian Solid-State Circuits Conference Solid-State Circuits Conference, 2008. A-SSCC '08. IEEE Asian. :245-248 Nov, 2008

Relation: 2008 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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3

A 2.3-mW 0.01-mm $^{\text{2}}$ 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS

المؤلفون: Yongjo Kim, Keun-Soo Song, Dongkyun Kim, SeongHwan Cho

المصدر: IEEE Transactions on Circuits and Systems II: Express Briefs. 64:397-401

مصطلحات موضوعية: Computer science, 020208 electrical & electronic engineering, 02 engineering and technology, Feedback loop, Chip, Multiplexing, Phase-locked loop, CMOS, Logic gate, Delay-locked loop, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Electrical and Electronic Engineering, Dram

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::94cf8353a91774e2263947f0eb8f4c11
https://doi.org/10.1109/tcsii.2016.2569441

4

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques

المصدر: IEEE Journal of Solid-State Circuits. 50:1945-1959

مصطلحات موضوعية: Computer science, Clock rate, Bandwidth (signal processing), Electronic engineering, Memory rank, Electrical and Electronic Engineering, Chip, Electrical efficiency, Dram, Voltage

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::bd3ecdd5a1b8474a68f8bb2d19ea9028
https://doi.org/10.1109/jssc.2015.2429588

5

A floating tap termination scheme with inverted DBI AC and floating tap forcing technique for high-speed low-power signaling

المؤلفون: Dong-Wook Jang, Dae-Han Kwon, Kim Woong-Rae, Hee-Woong Song, Keun-Soo Song, Hae-Kang Jung, Hong-Joo Song, Joo-Hwan Cho, Jonghoon Oh, Kyung-hoon Kim

المصدر: 2017 Symposium on VLSI Circuits.

مصطلحات موضوعية: Dc current, Engineering, Forcing (recursion theory), Power demand, business.industry, Electronic engineering, Data bus inversion, Signal integrity, Unbalanced data, business, Electrical efficiency, Electrical impedance

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::61c4437d90332c7a36805ec4af255767
https://doi.org/10.23919/vlsic.2017.8008477

6

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications

المؤلفون: Sang-Kwon Lee, Hyungsoo Kim, Hae-Kang Jung, Jeonghun Lee, Jaemo Yang, Jongjoo Shim, Yunsaing Kim, Dongkyun Kim, Hyuk Lee, Hyeongjun Ko, Keun-Soo Song, Taek-Sang Song

المصدر: VLSIC

مصطلحات موضوعية: Engineering, business.industry, Interface (computing), Transistor, Transmitter, Process (computing), Equalization (audio), Multiplexer, law.invention, law, Electronic engineering, business, Electrical efficiency, Dram

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::f9d535b1fb106391d31592b33742c4b4
https://doi.org/10.1109/vlsic.2015.7231255

7

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

المصدر: ISSCC

مصطلحات موضوعية: Engineering, business.industry, Hardware_PERFORMANCEANDRELIABILITY, Noise (electronics), Phase-locked loop, Voltage-controlled oscillator, CMOS, Delay-locked loop, Hardware_INTEGRATEDCIRCUITS, Charge pump, Electronic engineering, business, Dram, Jitter

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::d3e2e286b65c62e3836c96bc0c173b61
https://doi.org/10.1109/isscc.2009.4977347

8

A single-loop DLL using an OR-AND duty-cycle correction technique

المؤلفون: Jin-Hong Ahn, Byong-Tae Chung, Cheul-Hee Koo, Keun-Soo Song, Young-Jung Choi, Kwan-Weon Kim, Nak-Kyu Park

المصدر: 2008 IEEE Asian Solid-State Circuits Conference.

مصطلحات موضوعية: Engineering, CMOS, business.industry, Duty cycle, Detector, Spice, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Error detection and correction, business, Block (data storage), Power (physics), Jitter

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::d929252200426ff6562ccb2dfb32320b
https://doi.org/10.1109/asscc.2008.4708774

9

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

المصدر: ISSCC

مصطلحات موضوعية: Synchronous circuit, Engineering, CMOS, Duty cycle, Clock domain crossing, business.industry, Detector, Dual loop, Electronic engineering, business, Dram, Dual (category theory)

URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::4b6e0d0fb4f9670bb5ee6c1eea2be2c2
https://doi.org/10.1109/isscc.2008.4523167

10

مؤتمر

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

المصدر: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p282-613, 332p

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