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1Hardware Flexible Systolic Architecture for Convolution Accelerator in Convolutional Neural Networks
المصدر: 2022 45th International Conference on Telecommunications and Signal Processing (TSP).
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::4589d09a4d397f123457cbaafcfc47e2
https://doi.org/10.1109/tsp55681.2022.9851310 -
2دورية أكاديمية
المؤلفون: Moisés Arredondo-Velázquez, Paulo Aaron Aguirre-Álvarez, Alfredo Padilla-Medina, Alejandro Espinosa-Calderon, Juan Prado-Olivarez, Javier Diaz-Carmona
المصدر: Applied Sciences, Vol 13, Iss 1, p 93 (2022)
مصطلحات موضوعية: convolutional neural networks (CNN), hardware accelerators, systolic array, field programmable gate arrays (FPGA), embedded systems, Technology, Engineering (General). Civil engineering (General), TA1-2040, Biology (General), QH301-705.5, Physics, QC1-999, Chemistry, QD1-999
وصف الملف: electronic resource