يعرض 1 - 10 نتائج من 10 نتيجة بحث عن '"Shin-Deok Kang"', وقت الاستعلام: 0.87s تنقيح النتائج
  1. 1
    مؤتمر
    A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL

    المؤلفون: Dong Uk Lee, Hyun Woo Lee, Ki Chang Kwean, Young Kyoung Choi, Hyong Uk Moon, Seung Wook Kwack, Shin Deok Kang, Kwan Weon Kim, Yong Ju Kim, Young Jung Choi, Moran, P., Jin Hong Ahn, Joong Sik Kih

    المصدر: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International. :547-556 2006

    Relation: 2006 IEEE International Solid State Circuits Conference

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  2. 2
    مؤتمر
    A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

    المؤلفون: Lee, Hyun-Woo, Yun, Won-Joo, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Lee, Dong-Uk, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Park, Nak-Kyu, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung

    المصدر: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. :140-141,141a Feb, 2009

    Relation: 2009 IEEE International Solid-State Circuits Conference - (ISSCC)

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  3. 3
    A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS

    المؤلفون: Hyung-Wook Moon, Won-Joo Yun, Jae-Suck Kang, Sujeong Sim, Sang-hoon Shin, Seung-Wook Kwack, Hyun-woo Lee, Shin-Deok Kang, Kwan-Weon Kim, Jong-Jin Lee, Hyeng-Ouk Lee, Won Jun Choi, Nak-Kyu Park, Byong-Tae Chung, Young-Kyoung Choi, Hyang-Hwa Choi, Jung-Woo Lee, Young-Jung Choi, Keun-Soo Song, Dong Uk Lee, Ki-Han Kim, Jin-Hong Ahn, Ji Yeon Yang, Young Ju Kim

    المصدر: ISSCC

    مصطلحات موضوعية: Engineering, business.industry, Hardware_PERFORMANCEANDRELIABILITY, Noise (electronics), Phase-locked loop, Voltage-controlled oscillator, CMOS, Delay-locked loop, Hardware_INTEGRATEDCIRCUITS, Charge pump, Electronic engineering, business, Dram, Jitter

    URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::d3e2e286b65c62e3836c96bc0c173b61
    https://doi.org/10.1109/isscc.2009.4977347

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  4. 4
    A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology

    المؤلفون: Sang-hoon Shin, Dongsuk Shin, Shin Deok Kang, Won-Joo Yun, Keun Soo Song, Ye Seok Yang, Dong Uk Lee, Won Jun Choi, Jin-Hong Ahn, Hyang Hwa Choi, Hyeng Ouk Lee, Nak Kyu Park, Sujeong Sim, Seung Wook Kwack, Young Ju Kim, Ji Yeon Yang, Hyung Wook Moon, Hyun-woo Lee, Kwan-Weon Kim, Young Kyoung Choi, Jung-Woo Lee, Young Jung Choi

    المصدر: ISSCC

    مصطلحات موضوعية: Synchronous circuit, Engineering, CMOS, Duty cycle, Clock domain crossing, business.industry, Detector, Dual loop, Electronic engineering, business, Dram, Dual (category theory)

    URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::4b6e0d0fb4f9670bb5ee6c1eea2be2c2
    https://doi.org/10.1109/isscc.2008.4523167

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  5. 5
    Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface

    المؤلفون: Ye Seok Yang, Dong Uk Lee, Jung-Woo Lee, Shin Deok Kang, Young Jung Choi, Hyun-woo Lee, Kwan-Weon Kim, Sang-hoon Shin, Young Kyoung Choi, Nak Kyu Park, Won-Joo Yun, Hyeong Ouk Lee, Seung Wook Kwack

    المصدر: ISSCC

    مصطلحات موضوعية: Engineering, business.industry, Slew rate, Hardware_PERFORMANCEANDRELIABILITY, Driver circuit, Capacitance, Hardware_INTEGRATEDCIRCUITS, Calibration, Electronic engineering, business, Electrical impedance, Dram, Shmoo plot, Data transmission

    URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::a44c495b7d801bb6c899f6bd914cc964
    https://doi.org/10.1109/isscc.2008.4523166

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  6. 6
    A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM

    المؤلفون: Young-Kyoung Choi, Won-Joo Yun, Ki-Chang Kwean, Won Jun Choi, Seung-Wook Kwack, Young-Jung Choi, Shin-Deok Kang, Sang-hoon Shin, Joong-Sik Kih, Hyong-Uk Moon, Hyun-woo Lee, Kwan-Weon Kim, Hyang-Hwa Choi, Hyeng-Ouk Lee, Nak-Kyu Park, Jung-Woo Lee, Young Ju Kim, Dong Uk Lee, Jin-Hong Ahn, Ye-Seok Yang

    المصدر: 2006 IEEE Asian Solid-State Circuits Conference.

    مصطلحات موضوعية: Engineering, business.industry, Duty cycle, Replica, Controller (computing), Low-power electronics, Process (computing), Electronic engineering, business, Dram, Block (data storage), Power (physics)

    URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::6ce5ff40096b319a115e06fb9c94ea05
    https://doi.org/10.1109/asscc.2006.357916

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  7. 7
    مؤتمر
    A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.

    المؤلفون: Won-Joo Yun, Hyun Woo Lee, Dongsuk Shin, Shin Deok Kang, Ji Yeon Yang, Hyeng Ouk Lee, Dong Uk Lee, Sujeong Sim, Young Ju Kim, Won Jun Choi, Keun Soo Song, Sang Hoon Shin, Hyang Hwa Choi, Hyung Wook Moon, Seung Wook Kwack, Jung Woo Lee, Young Kyoung Choi, Nak Kyu Park, Kwan Weon Kim, Young Jung Choi

    المصدر: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p282-613, 332p

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  8. 8
    مؤتمر
    Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.

    المؤلفون: Dong Uk Lee, Shin Deok Kang, Nak Kyu Park, Hyun Woo Lee, Young Kyoung Choi, Jung Woo Lee, Seung Wook Kwack, Hyeong Ouk Lee, Won Joo Yun, Sang Hoon Shin, Kwan Weon Kim, Young Jung Choi, Ye Seok Yang

    المصدر: 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2008, p280-613, 334p

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  9. 9
    مؤتمر
    A Low Power Digital DLL with Wide Locking Range for 3Gbps 512Mb GDDR3 SDRAM.

    المؤلفون: Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, Seung-Wook Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih, Ye-Seok Yang

    المصدر: 2006 IEEE Asian Solid-State Circuits Conference; 2006, p323-326, 4p

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  10. 10
    مؤتمر
    A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.

    المؤلفون: Hyun-Woo Lee, Won-Joo Yun, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Dong-Uk Lee, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Nak-Kyu Park

    المصدر: 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers; 2009, p140-141a, 3p

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