التفاصيل البيبلوغرافية
| العنوان: |
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. |
| المؤلفون: |
Uksong Kang, Hoe-Ju Chung, Seongmoo Heo, Duk-Ha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Soo-Ho Cha, Jaesung Ahn, DukMin Kwon, Jae-Wook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo Sun Choi, Changhyun Kim |
| المصدر: |
IEEE Journal of Solid-State Circuits; Jan2010, Vol. 45 Issue 1, p111-119, 9p |
| مصطلحات موضوعية: |
DYNAMIC random access memory, NARROW gap semiconductors, BIT rate, SPEED limits, QUANTITATIVE research |
| مستخلص: |
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to <100 mV even if all 4 ranks are refreshed every clock cycle consecutively. [ABSTRACT FROM AUTHOR] |
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