التفاصيل البيبلوغرافية
| العنوان: |
A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion. |
| المؤلفون: |
Chia-Pei Chen, Ming-Jen Yang, Hsun-Hsiu Huang, Tung-Ying Chiang, Jheng-Liang Chen, Ming-Chieh Chen, Kuei-Ann Wen |
| المصدر: |
IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Dec2009, Vol. 56 Issue 12, p2738-2748, 11p |
| مصطلحات موضوعية: |
LOW voltage integrated circuits, COMPLEMENTARY metal oxide semiconductors, FREQUENCY modulation detectors, BANDPASS filters, FREQUENCY synthesizers, RADIO transmitter-receivers |
| مستخلص: |
A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the transmitter, the open-loop VCO modulation is adopted to save hardware and power consumption. The transmitter frequency drift in open-loop modulation and frequency offset between the receiver and the transmitter can be easily resolved by the proposed receiver architecture. All required building blocks of the proposed transceiver, except a RF matching network and a crystal, were implemented on a 4-mm² chip by a 0.18-μm CMOS process. The receiver achieves -89-dBm sensitivity at 0.1% BER with 1-Mb/s data rate, and the transmitter delivers up to 0-dBm output power. The receiver and transmitter consume 13.3 mA and 10.7 mA, respectively, from a 1.8-V power supply. [ABSTRACT FROM AUTHOR] |
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