An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.

التفاصيل البيبلوغرافية
العنوان: An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion.
المؤلفون: Jeong-Don Ihm, Seung-Jun Bae, Kwang-II Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Su-Jin Park
المصدر: 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers; 2007, p492-617, 126p
قاعدة البيانات: Complementary Index
الوصف
ردمك:9781424408535
DOI:10.1109/ISSCC.2007.373509