دورية
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization
العنوان: | A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization |
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المؤلفون: | Jin, Jahoon, Lee, Soo-Min, Min, Kyunghwan, Ju, Sodam, Lim, Jihoon, Yook, Jisu, Lee, Jihoon, Chae, Hyunsu, Kang, Kwonwoo, Hong, Yunji, Jeong, Yeongcheol, Park, Sung-Sik, Kim, Sang-Ho, Lee, Jongwoo, Kim, Joonsuk, Kwak, Sung Ung |
المصدر: | IEEE Journal of Solid-State Circuits; January 2024, Vol. 59 Issue: 1 p184-195, 12p |
مستخلص: | This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20 |
قاعدة البيانات: | Supplemental Index |
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