التفاصيل البيبلوغرافية
| العنوان: |
A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme |
| المؤلفون: |
Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, Dongsu Lee, Hangyun Jung, Hanki Jeoung, Ki-Won Lee, Junsuk Park, Jongeun Lee, Byunghyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byungsick Moon, Jung-Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo Sun Choi, Kyung Seok Oh |
| المصدر: |
2012 IEEE International Solid-State Circuits Conference. |
| بيانات النشر: |
IEEE, 2012. |
| سنة النشر: |
2012 |
| مصطلحات موضوعية: |
DDR4 SDRAM, Scheme (programming language), Power demand, CMOS, business.industry, Computer science, Fetch, business, Error detection and correction, computer, Computer hardware, Dual (category theory), computer.programming_language |
| URL الوصول: |
https://explore.openaire.eu/search/publication?articleId=doi_________::067b573eacb4ae8744e734ab6cf63573
https://doi.org/10.1109/isscc.2012.6176868 |
| رقم الأكسشن: |
edsair.doi...........067b573eacb4ae8744e734ab6cf63573 |
| قاعدة البيانات: |
OpenAIRE |
