An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

التفاصيل البيبلوغرافية
العنوان: An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme
المؤلفون: null Kyu-hyoun Kim, null Uksong Kang, null Hoe-Ju Chung, null Duk-Ha Park, null Woo-Seop Kim, null Young-Chan Jang, null Moonsook Park, null Hoon Lee, null Jin-Young Kim, null Jung Sunwoo, null Hwan-Wook Park, null Hyun-Kyung Kim, null Su-Jin Chung, null Jae-Kwan Kim, null Hyung-Seuk Kim, null Kee-Won Kwon, null Young-Taek Lee, null Joo Sun Choi, null Changhyun Kim
المصدر: 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
بيانات النشر: IEEE, 2006.
سنة النشر: 2006
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::b9f8b2954c6651dbe8e4120ad7fcd6cb
https://doi.org/10.1109/isscc.2006.1696089
رقم الأكسشن: edsair.doi...........b9f8b2954c6651dbe8e4120ad7fcd6cb
قاعدة البيانات: OpenAIRE