When forming microscopic patterns in sub-0.17/sup /spl middot// /spl middot/process, in order to secure stable DOF margin at photo lithography, inorganic SiO/sub x/N/sub y/ is often used for antireflective coating (ARC) for patterning line and contact hole through depositing plasma CVD method. In our gigabit process, SiO/sub x/N/sub y/ ARC is also being used for gate fabrication in deep-UV lithography. We've been leaving ARC on gate in order to secure insulation margin between gate and SAC (Self Aligned Contact) poly-Si pad. However there have occasionally been malfunctions in devices due to the generation of leakage current through ARC on gate between SAC pads. In this paper we discuss never-been-reported leakage current behaviors due to remained SiO/sub x/N/sub y/ ARC on gate in sub-0.17/sup /spl middot// /spl middot/gigabit process with a point of view of the effect of process parameters (the high frequency (HF) power of ARC deposition, metal contamination and implanted phosphorus ions) and the method of improving failure.
