13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry

التفاصيل البيبلوغرافية
العنوان:	13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry
المؤلفون:	Yang, Jaehyeok, Ko, Hyeongjun, Kim, Kyunghoon, Park, Hyunsu, Park, Jihwan, Kang, Ji-Hyo, Cha, Jinyoup, Kim, Seongjin, Kim, Youngtaek, Park, Minsoo, Lee, Gangsik, Lee, Keonho, Lee, Sanghoon, Jeon, Gyunam, Jeong, Sera, Joo, Yongsuk, Cha, Jaehoon, Hwang, Seonwoo, Kim, Boram, Byeon, Sangyeon, Lee, Sungkwon, Park, Hyeonyeol, Cho, Joohwan, Kim, Jonghwan
المصدر:	2024 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2024 IEEE International. 67:232-234 Feb, 2024
Relation:	2024 IEEE International Solid-State Circuits Conference (ISSCC)
قاعدة البيانات:	IEEE Xplore Digital Library