Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator : *A joint development project of Green Mountain Semiconduct Inc. (GMS) and Non-Von LLC

التفاصيل البيبلوغرافية
العنوان:	Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator : *A joint development project of Green Mountain Semiconduct Inc. (GMS) and Non-Von LLC
المؤلفون:	Hokenmaier, W., Jurasek, R., Bowen, E., Granger, R., Odom, D.
المصدر:	2024 IEEE 33rd Microelectronics Design & Test Symposium (MDTS) Microelectronics Design & Test Symposium (MDTS), 2024 IEEE 33rd. :1-6 May, 2024
Relation:	2024 IEEE 33rd Microelectronics Design & Test Symposium (MDTS)
قاعدة البيانات:	IEEE Xplore Digital Library