An FPGA Based Emulation of Source Synchronous Protocol-Aware Timing Stress Test

التفاصيل البيبلوغرافية
العنوان: An FPGA Based Emulation of Source Synchronous Protocol-Aware Timing Stress Test
المؤلفون: Manda, P R R K Tirumalesu, Rakesh, Vinodh, Ghanta, Vasavi, Raju, Jagadish Raju Krishna
المصدر: 2024 IEEE 8th International Test Conference India (ITC India) Test Conference India (ITC India), 2024 IEEE 8th International. :1-6 Jul, 2024
Relation: 2024 IEEE 8th International Test Conference India (ITC India)
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:9798350352597
تدمد:28338391
DOI:10.1109/ITCIndia62949.2024.10651976