A skewed repeater bus architecture for on-chip energy reduction in microprocessors

التفاصيل البيبلوغرافية
العنوان: A skewed repeater bus architecture for on-chip energy reduction in microprocessors
المؤلفون: Khellah, M., Ghoneima, M., Tschanz, J., Yibin Ye, Kurd, N., Barkatullah, J., Nimmagadda, S., Ismail, Y., De, V.
المصدر: 2005 International Conference on Computer Design Computer Design Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on. :253-257 2005
Relation: Proceedings. 2005 International Conference on Computer Design
قاعدة البيانات: IEEE Xplore Digital Library