مؤتمر
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS
| العنوان: | A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS |
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| المؤلفون: | Lee, Hyun-Woo, Yun, Won-Joo, Young-Kyoung Choi, Hyang-Hwa Choi, Jong-Jin Lee, Ki-Han Kim, Shin-Deok Kang, Ji-Yeon Yang, Jae-Suck Kang, Hyeng-Ouk Lee, Lee, Dong-Uk, Sujeong Sim, Young-Ju Kim, Won-Jun Choi, Keun-Soo Song, Sang-Hoon Shin, Hyung-Wook Moon, Seung-Wook Kwack, Jung-Woo Lee, Park, Nak-Kyu, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Byong-Tae Chung |
| المصدر: | 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. :140-141,141a Feb, 2009 |
| Relation: | 2009 IEEE International Solid-State Circuits Conference - (ISSCC) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 9781424434589 |
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| تدمد: | 01936530 23768606 |
| DOI: | 10.1109/ISSCC.2009.4977347 |