دورية أكاديمية
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration
| العنوان: | Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration |
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| المؤلفون: | Niitsu, K., Kohama, Y., Sugimori, Y., Kasuga, K., Osada, K., Irie, N., Ishikuro, H., Kuroda, T. |
| المصدر: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 18(8):1238-1243 Aug, 2010 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 10638210 15579999 |
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| DOI: | 10.1109/TVLSI.2009.2020724 |