دورية أكاديمية
Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
| العنوان: | Design and Iso-Area $V_{\min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS |
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| المؤلفون: | Chang, M.-H., Chiu, Y.-T., Hwang, W. |
| المصدر: | IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 59(7):429-433 Jul, 2012 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 15497747 15583791 |
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| DOI: | 10.1109/TCSII.2012.2198984 |