Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias

التفاصيل البيبلوغرافية
العنوان:	Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias
المؤلفون:	Agrawal, V., Kepler, N., Kidd, D., Krishnan, G., Leshner, S., Bakishev, T., Zhao, D., Ranade, P., Roy, R., Wojko, M., Clark, L., Rogenmoser, R., Hori, M., Ema, T., Moriwaki, S., Tsuruta, T., Yamada, T., Mitani, J., Wakayama, S.
المصدر:	Proceedings of the IEEE 2013 Custom Integrated Circuits Conference Custom Integrated Circuits Conference (CICC), 2013 IEEE. :1-4 Sep, 2013
Relation:	2013 IEEE Custom Integrated Circuits Conference - CICC 2013
قاعدة البيانات:	IEEE Xplore Digital Library