دورية أكاديمية
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
| العنوان: | A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation |
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| المؤلفون: | Oh, T.-Y., Chung, H., Park, J.-Y., Lee, K.-W., Oh, S., Doo, S.-Y., Kim, H.-J., Lee, C., Kim, H.-R., Lee, J.-H., Lee, J.-I., Ha, K.-S., Choi, Y., Cho, Y.-C., Bae, Y.-C., Jang, T., Park, C., Park, K., Jang, S., Choi, J. S. |
| المصدر: | IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 50(1):178-190 Jan, 2015 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 00189200 1558173X |
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| DOI: | 10.1109/JSSC.2014.2353799 |