التفاصيل البيبلوغرافية
| العنوان: |
A 0.5?9.5-GHz, 1.2- \mu \texts Lock-Time Fractional-N DPLL With ?1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling. |
| المؤلفون: |
Ahmad, Fazil, Unruh, Greg, Iyer, Amrutha, Su, Pin-En, Abdalla, Sherif, Shen, Bo, Chambers, Mark, Fujimori, Ichiro |
| المصدر: |
IEEE Journal of Solid-State Circuits; Jan2017, Vol. 52 Issue 1, p21-32, 12p |
| مصطلحات موضوعية: |
PHASE-locked loops, THERMAL management (Electronic packaging), ELECTRIC oscillators |
| مستخلص: |
A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast lock time of 1.2 \mu \texts without any frequency overshoots and a nonlinear DCO that enables a wide frequency range of 0.5–9.5 GHz and a low period jitter of ±1.25%UI p-p with a single wideband tuning. With this proposed PLL architecture, SoC can continue its operation without any interruption caused by frequency overshoots during power and thermal management techniques like dynamic core-count scaling and dynamic voltage frequency scaling. The PLL achieves 0.45 ps rms period jitter at 3.25 GHz in fractional-N mode operation, while consuming a total power of 7.1 mW. [ABSTRACT FROM PUBLISHER] |
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