التفاصيل البيبلوغرافية
| العنوان: |
A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration. |
| المؤلفون: |
Fenouillet-Beranger, C., Brunet, L., Batude, P., Brevard, L., Garros, X., Casse, M., Lacord, J., Sklenard, B., Acosta-Alba, P., Kerdiles, S., Tavernier, A., Vizioz, C., Besson, P., Gassilloud, R., Pedini, J.-M., Kanyandekwe, J., Mazen, F., Magalhaes-Lucas, A., Cavalcante, C., Bosch, D. |
| المصدر: |
IEEE Transactions on Electron Devices; Jul2021, Vol. 68 Issue 7, p3142-3148, 7p |
| مصطلحات موضوعية: |
LOW temperatures, COMPLEMENTARY metal oxide semiconductors, SURFACE preparation, VERY large scale circuit integration, THERMAL stability, FIELD-effect transistors |
| مستخلص: |
In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low-k (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted. [ABSTRACT FROM AUTHOR] |
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