التفاصيل البيبلوغرافية
العنوان: |
Demonstration of scaling and monolithic stacking for higher integration of integrated circuit using c -axis aligned crystalline oxide semiconductor FET. |
المؤلفون: |
Sawai, Hiromi, Kurata, Motomu, Murakawa, Tsutomu, Ando, Yoshinori, Fukushima, Kunihiro, Eto, Ryota, Sasagawa, Shinya, Sugaya, Kentaro, Hodo, Ryota, Mizuguchi, Toshiki, Komura, Yusuke, Kunitake, Hitoshi, Takagi, Shinichi, Yamazaki, Shunpei |
المصدر: |
Japanese Journal of Applied Physics; May2024, Vol. 63 Issue 5, p1-5, 5p |
مستخلص: |
C -axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs exhibit extremely low off-state leakage current and thus are suitable for low-power devices. Furthermore, CAAC-OS FETs can be integrated in the back end of line process and are promising as memory devices. For higher integration using the CAAC-OS FETs, we examined scaling and monolithic stacking. In addition, we present a 3D dynamic random access memory prototype, which is formed using three-layer monolithically stacked CAAC-OS FETs on a Si-CMOS and exhibits long-term data retention owing to the ultralow off-leakage current. These techniques will contribute to higher speed and integration of memory devices. [ABSTRACT FROM AUTHOR] |
|
Copyright of Japanese Journal of Applied Physics is the property of IOP Publishing and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) |
قاعدة البيانات: |
Complementary Index |