مؤتمر
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
| العنوان: | Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. |
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| المؤلفون: | Yasufuku, T., Iida, S., Fuketa, H., Hirairi, K., Nomura, M., Takamiya, M., Sakurai, T. |
| المصدر: | 2011 International Symposium on Low Power Electronics & Design (ISLPED); 2011, p21-26, 6p |
| قاعدة البيانات: | Complementary Index |
Full Text Finder | ردمك: | 9781612846583 |
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| DOI: | 10.1109/ISLPED.2011.5993598 |