A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization

التفاصيل البيبلوغرافية
العنوان:	A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization
المؤلفون:	Jin, Jahoon, Lee, Soo-Min, Min, Kyunghwan, Ju, Sodam, Lim, Jihoon, Yook, Jisu, Lee, Jihoon, Chae, Hyunsu, Kang, Kwonwoo, Hong, Yunji, Jeong, Yeongcheol, Park, Sung-Sik, Kim, Sang-Ho, Lee, Jongwoo, Kim, Joonsuk, Kwak, Sung Ung
المصدر:	IEEE Journal of Solid-State Circuits; January 2024, Vol. 59 Issue: 1 p184-195, 12p
مستخلص:	This article presents a 16-Gb/s/pin 0.764-pJ/b single-ended four-level pulse-amplitude modulation (PAM-4) transceiver in a 4-nm CMOS process. A switching-jitter compensation technique is proposed in the receiver (RX) to improve timing margins from 0.31 to 0.37 UI at 16 Gb/s, as it adjusts transition slope of the front-end outputs. To compensate for signal-to-noise ratio (SNR) degradation in a PAM-4 signal, relaxed impedance matching is used, where 20 $\Omega $ is used as a transmitter (TX) impedance instead of 50 $\Omega $ . To maximize eye openings further, fractionally spaced feedforward equalization (FS-FFE) is used with a tap spacing of 0.8 UI. The relaxed termination scheme along with FS-FFE improves eye openings by 2.25 times compared with the conventional design using a 50- $\Omega $ TX impedance with 1-UI spacing FFE.
قاعدة البيانات:	Supplemental Index

الوصف
تدمد:	00189200 1558173X
DOI:	10.1109/JSSC.2023.3319637