The speed of any processor largely depends on the cache memory that it incorporates and the cache memory is predominantly made up of Static Random Access Memory (SRAM) cells. Therefore, with the technology shrinking every year, it is becoming essential to improve its reliability. This paper presents a qualitative analysis of a 6T Static Random Access Memory (SRAM) cell when it has been induced with noise in the inverter latch and also in the power supply. The analysis has been done in 180nm CMOS technology in terms of Static Noise Margin (SNM), Write Margin, and Write time on the induction of both the noises. The Simulation results show that the percentage difference of Noise Margin between noise-induced SRAM and that along with fluctuating power supply environment is 3.27%, 4.35%, and 4.74% in read, hold, and write operations. Also a difference of 50ps in the Write Time of the cell.
