Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22/spl times/6.6 mm/sup 2/. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.
