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Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

التفاصيل البيبلوغرافية
العنوان:	Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process
المؤلفون:	Y. Okuno, Marc Aoulaiche, Naoto Horiguchi, C. Ortolland, T. Y. Hoffmann, Christoph Kerner, C. Stapelmann, Peter Verheyen
المصدر:	IEEE Transactions on Electron Devices. 56:1690-1697
بيانات النشر:	Institute of Electrical and Electronics Engineers (IEEE), 2009.
سنة النشر:	2009
مصطلحات موضوعية:	Computer science, Strained silicon, Hardware_PERFORMANCEANDRELIABILITY, Memorization, Electronic, Optical and Magnetic Materials, PMOS logic, CMOS, Logic gate, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Electrical and Electronic Engineering, NMOS logic, Maskless lithography, Hardware_LOGICDESIGN
الوصف:	In this paper, a comprehensive work toward the understanding of the stress memorization technique (SMT) is presented. The effects of the SMT upon PMOS and NMOS device performance are investigated and explained. A novel low-cost solution for a maskless SMT integration into advanced CMOS technologies is proposed, and additional device results examining the compatibility of SMT with fully silicided and metal inserted polysilicon gates are presented.
تدمد:	0018-9383
URL الوصول:	https://explore.openaire.eu/search/publication?articleId=doi_________::0cf85ab5ab8df798f01cfd2b3af31c13 https://doi.org/10.1109/ted.2009.2024021
حقوق:	CLOSED
رقم الأكسشن:	edsair.doi...........0cf85ab5ab8df798f01cfd2b3af31c13
قاعدة البيانات:	OpenAIRE

الوصف
تدمد:	00189383