Vertical III–V nanowire transistors and CMOS circuits on Si

التفاصيل البيبلوغرافية
العنوان: Vertical III–V nanowire transistors and CMOS circuits on Si
المؤلفون: Johannes Svensson, Lars-Erik Wernersson, Daniel Jacobsson, Anil W. Dey
المصدر: 2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS).
بيانات النشر: IEEE, 2016.
سنة النشر: 2016
مصطلحات موضوعية: Materials science, Silicon, business.industry, Transistor, Nanowire, chemistry.chemical_element, Nanotechnology, NAND logic, Epitaxy, law.invention, CMOS, chemistry, law, Optoelectronics, Metalorganic vapour phase epitaxy, business, Electronic circuit
الوصف: III–V integration on Si is one of the most attractive options to extend future CMOS circuits. However, direct material integration by epitaxial growth is challenging mainly due to the large lattice mismatch. Here we present a novel technique that enables InAs and GaSb nanowires to be grown on Si substrates in the same MOVPE run. By reducing the Au seed size, the nucleation of GaSb can be suppressed resulting in InAs-GaSb as well as InAs nanowires. Vertical p and n-type MOSFETs, inverters and NAND gates have been fabricated and electrically characterized demonstrating the suitability of our method for large scale III–V MOSFET circuits on Si.
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::121203f6d6a643a08dc7e35f032cf8a5
https://doi.org/10.1109/iciprm.2016.7528556
رقم الأكسشن: edsair.doi...........121203f6d6a643a08dc7e35f032cf8a5
قاعدة البيانات: OpenAIRE