A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
| العنوان: | A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation |
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| المؤلفون: | Marco Cusmai, Daniele Baldi, Francesco Svelto, Colin Weltin-Wu, Enrico Temporiti |
| المصدر: | ISSCC |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2010. |
| سنة النشر: | 2010 |
| مصطلحات موضوعية: | Frequency synthesizer, Engineering, business.industry, Noise reduction, Electrical engineering, Phase-locked loop, Time-to-digital converter, CMOS, Phase noise, Electronic engineering, Dither, Electrical and Electronic Engineering, Wideband, business |
| الوصف: | The digital-intensive approach to frequency synthesis embodied by the ADPLL [1] has seen a flurry of recent activity [2–4] due to benefits in both performance (programmability, noise immunity) and integration (area reduction, easy porting) in nanoscale CMOS versus the traditional analog approach. However, the quantization of voltage and time—intrinsic to sampled-data systems—leads to problems with spurious tones and in-band phase noise the former of which has hitherto excluded the ADPLL from stringent wideband wireless applications. Low in-band phase noise requires a high-resolution TDC, whereas the dominant source of in-band spurious tones in an ADPLL is the TDC's nonlinearity, which is not directly coupled with TDC resolution. Although effective techniques to mitigate TDC nonlinearities have been proposed in [2,3], with worst-spur performance around −45dBc they are still far from analog state-of-the-art [6]. |
| تدمد: | 1558-173X 0018-9200 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::13b85237366a85d451c8a99c25abfb18 https://doi.org/10.1109/jssc.2010.2077370 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........13b85237366a85d451c8a99c25abfb18 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 1558173X 00189200 |
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