Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

التفاصيل البيبلوغرافية
العنوان: Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness
المؤلفون: Chuan-Ding Lin, Wei-Chen Chen, Tiao-Yuan Huang, Horng-Chih Lin
المصدر: IEEE Electron Device Letters. 30:644-646
بيانات النشر: Institute of Electrical and Electronics Engineers (IEEE), 2009.
سنة النشر: 2009
مصطلحات موضوعية: Fabrication, Materials science, Silicon, business.industry, Transistor, Nanowire, chemistry.chemical_element, Nanotechnology, engineering.material, Thermal conduction, Electronic, Optical and Magnetic Materials, law.invention, Polycrystalline silicon, chemistry, Etching (microfabrication), law, Hardware_INTEGRATEDCIRCUITS, engineering, Optoelectronics, Electrical and Electronic Engineering, business, Communication channel
الوصف: A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.
تدمد: 1558-0563
0741-3106
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::18d159c91912dbd0db61a18b429d63f5
https://doi.org/10.1109/led.2009.2018493
حقوق: CLOSED
رقم الأكسشن: edsair.doi...........18d159c91912dbd0db61a18b429d63f5
قاعدة البيانات: OpenAIRE