A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
| العنوان: | A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes |
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| المؤلفون: | Daisuke Hashimoto, Akihiro Nitayama, Daisaburo Takashima, Takeshi Hioka, Yoshiro Shimojo, Hidehiro Shiga, Yuki Yamada, Koji Yamakawa, Katsuhiko Hoya, Toyoki Taguchi, Shoichi Shimizu, Ryu Ogiwara, Hisaaki Nishimura, Tohru Ozaki, Yohji Watanabe, Shinichiro Shiratake, Sumiko Doumae, Iwao Kunishima, Tohru Furuyama, Tadashi Miyakawa, Hiroyuki Kanaya, Souichi Yamazaki, Shuso Fujii, Fumiyoshi Matsuoka, Yasushi Nagadomi, Ryo Fukuda, Ryosuke Takizawa, Yoshinori Kumura, Mitsumo Kawano, Susumu Shuto, Takeshi Hamamoto, Yoshihiro Minami, Kosuke Hatsuda |
| المصدر: | ISSCC |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2010. |
| سنة النشر: | 2010 |
| مصطلحات موضوعية: | Dynamic random-access memory, business.industry, Computer science, Bandwidth (signal processing), Electrical engineering, Octal, Integrated circuit, Ferroelectricity, Capacitance, law.invention, Non-volatile memory, Parasitic capacitance, law, Ferroelectric RAM, Electrical and Electronic Engineering, business, Cmos process, Computer hardware, Voltage |
| الوصف: | An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation. |
| تدمد: | 1558-173X 0018-9200 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::1fda70ed57de6c8e43a679a78faba8b0 https://doi.org/10.1109/jssc.2009.2034414 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........1fda70ed57de6c8e43a679a78faba8b0 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 1558173X 00189200 |
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