Design of Convolution Operation Accelerator based on FPGA

التفاصيل البيبلوغرافية
العنوان: Design of Convolution Operation Accelerator based on FPGA
المؤلفون: Xin Li, Haowei Zheng, Hui Li, Lei Kang
المصدر: 2020 2nd International Conference on Machine Learning, Big Data and Business Intelligence (MLBDBI).
بيانات النشر: IEEE, 2020.
سنة النشر: 2020
مصطلحات موضوعية: 010302 applied physics, Computer science, business.industry, Volume (computing), 02 engineering and technology, 01 natural sciences, Convolutional neural network, Convolution, Parallel processing (DSP implementation), Gate array, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Field-programmable gate array, business, Computer hardware
الوصف: Because of the high complexity and long time of CPU in convolution operation, the power consumption of GPU is high and it can not be deployed to small hardware devices. Field Programmable Logic Gate Array (FPGA) has parallelism and fast speed , Low power consumption and etc. Therefore, this paper proposes an improved RLeNet model, which optimizes model parameters and used a parallel technology to accelerate CNN hardware. The improved model parameter data volume is reduced to 3.2% of the original. Under the MNIST data set, the accuracy of the prediction result is 98.5%. Finally, on the Xilinx Nexys 4 DDR: Artix-7 development board, the prediction process of the convolutional neural network for handwriting recognition is implemented. When the system predicts with a 200MHz clock, the time to predict a picture is 31.8μs.
URL الوصول: https://explore.openaire.eu/search/publication?articleId=doi_________::29ddb6b0faadb9fcc9d042a949f5619a
https://doi.org/10.1109/mlbdbi51377.2020.00021
حقوق: CLOSED
رقم الأكسشن: edsair.doi...........29ddb6b0faadb9fcc9d042a949f5619a
قاعدة البيانات: OpenAIRE