To support the International Technology Roadmap for Semiconductors, equivalent thickness of the gate dielectric will need to be 1.0-1.5 nm by 2004. Due to increased power consumption, intrinsic device reliability, and circuit instabilities associated with SiO2 of this thickness, a high-permittivity gate dielectric (e.g., Si3N4, HfSixOy, ZrO2) with low leakage current and at least equivalent capacitance, performance, and reliability will be required. In this work, we investigate the stress-induced leakage current (SILC) at low field for both PMOS and NMOS with ultra-thin nitrided gate oxide with thickness of 1.6 nm. C-V measurements are used to extract the oxide thickness (Tox) and the substrate doping (Np), which must be corrected for this range of oxide thickness. The SILC generation kinetics after constant voltage stress is shown to be related to that of interface or near-interface oxide traps and to the concentration of the atoms of nitrogen near to the interface. Moreover, the situation in PMOS is just contrary to the NMOS. We attribute this to the different barrier lowering in conduction band and valence band.
