23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
التفاصيل البيبلوغرافية
العنوان:
23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power
High-speed and low-power techniques for the latest mobile DRAMs, such as LPDDR4/4X [1–3], have been developed to enable high-resolution displays, multiple cameras and 4G communication in mobile devices. However, DRAM with higher bandwidth and lower power consumption than LPDDR4X is indispensable to support 5G communication, on-device artificial intelligence and advanced driver assistance systems. In this paper, we present a 1st generation 10nm-class process LPDDR5. It includes novel schemes that increase the maximum bandwidth, such as WCK clocking and non-target ODT (NT-ODT). Power consumption is also reduced by low power schemes, such as dynamic voltage-frequency scaling (DVFS), an internal data-copy function called write-X and a deep-sleep mode (DSM).
