A 112 Gb/s PAM4 ADC based SERDES receiver is implemented on Intel 10 nm FinFET process. The receiver consists of a low noise analog front end (AFE), a 64-way time interleaved analog to digital converter (ADC) and a clock/data recovery (CDR) loop utilizing a 7GHz digitally controlled oscillator (DCO). The receiver supports long reach, -35 dB at Nyquist, channels with a pre-forward error correction bit error rate (BER) $\lt 1\mathrm{e} -6$ making it compatible with existing and projected Reed-Solomon FEC.
