SRAM stability during word line disturb (access disturb) is becoming a key constraint for V/sub DD/ scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/sub CRIT/. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V/sub T/ variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and array test can be used to verify that the stability target is met.
