Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security
| العنوان: | Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security |
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| المؤلفون: | Kai Ni, Matthew San Jose, Jeffrey Smith, Siddharth Joshi, Zephan M. Enciso, Suman Datta, Sourav Dutta, Benjamin Grisafe, Chloe Frentzel |
| المصدر: | IEEE Transactions on Electron Devices. 68:516-522 |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2021. |
| سنة النشر: | 2021 |
| مصطلحات موضوعية: | 010302 applied physics, Hardware security module, Computer science, business.industry, Overhead (engineering), Transistor, Reconfigurability, NAND gate, Integrated circuit, 01 natural sciences, Electronic, Optical and Magnetic Materials, law.invention, law, Logic gate, Embedded system, 0103 physical sciences, Electrical and Electronic Engineering, business, Hardware_LOGICDESIGN, Block (data storage) |
| الوصف: | Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC reverse engineering techniques have unleashed security threats such as intellectual property (IP) theft and insertion of hardware Trojans. In this article, we propose and implement a run-time reconfigurable camouflage logic technology based on ferroelectric field-effect transistor (FeFET). The technology simultaneously obfuscates design IP from zero-trust foundry and untrusted testing facility and thwarts reverse engineering and counterfeiting threat. We fabricate for the first time an eight FeFET-based circuit block and demonstrate in silico gate-level camouflaging by implementing three Boolean logic functions—NOR, NAND, and XNOR—in the same circuit topology using threshold voltage ( ${V}_{\text {T}}$ ) programming of FeFET. We perform circuit simulations using empirically calibrated models to estimate power, latency, and area overhead. Compared with recent proposal of programmable camouflage logic using hot-carrier injection (HCI), FeFET offers an overhead reduction of $2\times $ , $1.8\times $ , and $2.8\times $ in area, power, and delay, respectively. |
| تدمد: | 1557-9646 0018-9383 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::5cbf36c99503094fa6d3c089da044df9 https://doi.org/10.1109/ted.2020.3045380 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........5cbf36c99503094fa6d3c089da044df9 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 15579646 00189383 |
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