Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits
| العنوان: | Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits |
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| المؤلفون: | Krishnendu Chakrabarty, Sukeshwar Kannan, Abhishek Koneru |
| المصدر: | ACM Journal on Emerging Technologies in Computing Systems. 13:1-23 |
| بيانات النشر: | Association for Computing Machinery (ACM), 2017. |
| سنة النشر: | 2017 |
| مصطلحات موضوعية: | 010302 applied physics, Coupling, Fabrication, Materials science, Wafer bonding, business.industry, Transistor, 02 engineering and technology, Integrated circuit, Dielectric, 01 natural sciences, 020202 computer hardware & architecture, law.invention, Threshold voltage, Hardware and Architecture, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Optoelectronics, Electrical and Electronic Engineering, business, Scaling, Software |
| الوصف: | Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account. |
| تدمد: | 1550-4840 1550-4832 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::5e95058fce308ba760a6552aa888f702 https://doi.org/10.1145/3041026 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........5e95058fce308ba760a6552aa888f702 |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 15504840 15504832 |
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