We present a high-accuracy wideband quadrature clock generator (QCG) built in 5nm finFET CMOS. To achieve low power and high bandwidth, we employ an active poly phase filter (APPF) to generate the quadrature phases with 6dB gain boost and 30% bandwidth extension. The subsequent quadrature error corrector (QEC) and phase error detector (PED) corrects the APPF output phases with a phase interpolator (PI) to achieve rms phase jitter measured at 14GHz. The noise floor is below –138dBc/Hz at 1GHz offset. The QCG occupies 0.0017mm2 and consumes only 21mW on a 1.0V supply for a FoM of 1.16mW/GHz
