التفاصيل البيبلوغرافية
العنوان:
A CMOS RISC CPU with on-chip parallel cache
المؤلفون:
I. Krashinsky , D. Renfrow , J. Keller , John F. Shelton , K. Eshghi , S. Ranade , D. Weatherspoon , T. Alexander , P. Sabada , B. Ches , N. Noordeen , Kenneth K. Chan , N.S. Fiduccia , Michael A Buckley , E. Rashid , M. Ludwig , D. Goldberg , William R. Bryg , P. Ilgenfritz , J. Zheng , D. Cheung , C. Amir , A. Scherer , Eric Delano , F. Eatock , Gordon Kurpanek , R. Rajamani , Francis Schumacher
المصدر:
Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94 .
بيانات النشر:
IEEE, 2002.
سنة النشر:
2002
مصطلحات موضوعية:
Single chip , Hardware_MEMORYSTRUCTURES , Reduced instruction set computing , business.industry , Computer science , Interface (computing) , Transistor , Process (computing) , Hardware_PERFORMANCEANDRELIABILITY , Chip , law.invention , CMOS , law , Hardware_INTEGRATEDCIRCUITS , Cache , Risc cpu , business , Computer hardware , System bus
الوصف:
This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given. >
URL الوصول:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f51a76d90b93d53ae4244eaaa06ba04 https://doi.org/10.1109/isscc.1994.344666
رقم الأكسشن:
edsair.doi...........7f51a76d90b93d53ae4244eaaa06ba04
قاعدة البيانات:
OpenAIRE
