Gate leakage current is reduced up to 24% using a highly doped polysilicon gate/nitrided oxide gate stack. Interestingly, various factors that could affect the gate leakage current such as equivalent oxide thickness (EOT), overlap capacitance, gate dielectric reliability and sub-threshold voltage were found to be unrelated to the reduction in leakage current. Instead, an additional band offset due to an interfacial dipole at the highly doped polysilicon gate and nitrided oxide interface is proposed to explain the anti-intuitive leakage current reduction. This result implies that there is an optimal gate doping condition that will minimize the leakage current accounting a trade-off between the effect of the interfacial dipole and reliability.
