A high-dynamic-range (DR) CT ΔΣ modulator is required to relax the analog front-end filter design for wireless communication applications. To achieve high resolution (DR>90dB) and low power dissipation (FoMs>170dB), architecture selection and circuit techniques are the main design issues. In [1], a CT ΔΣ modulator embedded with a 2nd-order active filter and VGA is reported to extend the DR. However, the additional active filter results in a complicated architecture as well as extra area that is not preferred in advanced processes. An alternative method that improves the DR is to adopt the self-coupled noise-injection technique introduced in [2] to increase by one the order of the noise transfer function (NTF). Unfortunately, it requires an accurate clock cycle delay, which is only available in the DT ΔΣ modulator. Apart from DR considerations, power efficiency is still limited by the building block design. Conventional excess loop delay (ELD) compensation [1,3,4] is implemented by an inner DAC, which increases the power consumption and loads the last integrator with a large parasitic capacitance, especially for a multi-bit modulator. Therefore, a high-bandwidth opamp is required in the last integrator to alleviate the phase delay of the loop filter. Furthermore, to address the nonlinearity of a multi-bit DAC, 2nd-order dynamic element matching (DEM) is used in [5] to reduce data-dependent switching. The SFDR is still limited to 90dB. In this paper, CT self-coupling (CTSC), residual ELD compensation, and DAC linearity enhancement techniques are introduced to overcome these challenges. Our CT ΔΣ modulator achieves an SNDR of 90.4dB with an FoMs (SNDR) of 177.3dB in a 2.2MHz bandwidth.
