This paper presents for the first time a low-complexity high performance CMOS HK/MG process on planar bulk Si using a single dielectric / single metal gate stack and making use of dual-channel integration. Through the optimization of the Si 45 Ge 55 /Si cap deposition and the workfunction metal, high performance devices with balanced V t,sat (+0.12V, −0.16V) at scaled T inv ∼1nm and gate length L g ∼30nm are reported, leading to 17ps ring oscillators at 1µW/stage at Vdd=0.7V. Compatibility with gate last processing is also demonstrated.
