We describe a 3D integration process flow in which the vertical distance from the CMOS layer to the novel device layer is 100–1000 nm. This short distance effectively defines the process flow as a silicon CMOS process flow and allows for the use of silicon infrastructure in process and design. Progress has been made in demonstrating various pieces of III–V device integration into a foundry 0.18 µm process on 200 mm wafers.
