A novel work-function modulation technique for dual work-function (WF) metal gate for DRAM access device is investigated to minimize the leakage current in the access transistor. Gate Induced Drain Leakage (GIDL) is believed to be the most dominant off state leakage from storage node junction. Due to high doping in access device storage node side, lateral electric field near the storage node increases, which enhance the GIDL. Increased GIDL in DRAM puts limits on further scaling of DRAM cell. In this paper GIDL current dependence on gate metal work function has been investigated with TCAD simulation. A solution is proposed to minimize the GIDL current as well as possible fabrication techniques.
