Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs
| العنوان: | Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs |
|---|---|
| المؤلفون: | Francesco Svelto, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Enrico Temporiti |
| المصدر: | IEEE Transactions on Circuits and Systems I: Regular Papers. 57:2259-2268 |
| بيانات النشر: | Institute of Electrical and Electronics Engineers (IEEE), 2010. |
| سنة النشر: | 2010 |
| مصطلحات موضوعية: | Frequency synthesizer, Engineering, business.industry, Electrical engineering, Spurious tone, Phase-locked loop, Analog signal, Narrowband, CMOS, Phase noise, Electronic engineering, Electrical and Electronic Engineering, Wideband, business |
| الوصف: | As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in fractional-N all-digital phase-locked loops (ADPLLs) have proven them to be competitive with analog state of the art for narrowband applications, demonstrating excellent phase noise and achieving even traditionally difficult standards such as GSM. However, to achieve comparable high performance for wideband applications requires a reduction in fractional spurs. This paper provides a brief summary of ADPLL architectures, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique. Along the way, an efficient simulation model to predict fractional spur amplitude and frequency in ADPLLs is presented. The 3 GHz prototype operates from a flexible reference frequency, between 25 MHz-100 MHz, has in-band phase noise of -101 dBc/Hz with a decade of loop bandwidth programmability, and in-band spurs below -45 dBc. The synthesizer occupies 0.4 mm2 in 65 nm digital CMOS and consumes less than 10 mW from a 1.2 V supply. |
| تدمد: | 1558-0806 1549-8328 |
| URL الوصول: | https://explore.openaire.eu/search/publication?articleId=doi_________::ab1848d236a53d92755a1d7e05f5f4cf https://doi.org/10.1109/tcsi.2010.2071650 |
| حقوق: | CLOSED |
| رقم الأكسشن: | edsair.doi...........ab1848d236a53d92755a1d7e05f5f4cf |
| قاعدة البيانات: | OpenAIRE |
| تدمد: | 15580806 15498328 |
|---|